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專任教授


姓名

林群祐

職稱

副教授(獲本校優聘教授獎勵)

02-7749-3549

cy.lin@ntnu.edu.tw

個人網站

研究專長

積體電路之靜電放電防護設計、電治療積體電路與系統設計

研究成果

著作

  1. 2019. IEEE Trans. Device and Materials Reliability. ESD protection design for open-drain power amplifier in CMOS technology.
  2. 2019. IEEE Trans. Electron Devices. π-SCR device for broadband ESD protection in low-voltage CMOS technology.
  3. 2018. Microelectronics Reliability. Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology.
  4. 2018. IEEE Trans. Device and Materials Reliability. Low-C ESD protection design with dual resistor-triggered SCRs in CMOS technology.
  5. 2018. IEEE Trans. Circuits and Systems II: Express Briefs. Low-loss I/O pad with ESD protection for K/Ka-bands applications in nanoscale CMOS process.
  6. 2018. IEEE Trans. Electron Devices. On-chip HBM and HMM ESD protection design for RF applications in 40-nm CMOS process.
  7. 2017. Microelectronics Reliability. Investigation and application of vertical NPN devices for RF ESD protection in BiCMOS technology.
  8. 2017. IEEE Electron Device Letters. Resistor-triggered SCR device for ESD protection in high-speed I/O interface circuits.
  9. 2017. IEICE Electronics Express. Improved stacked-diode ESD protection in nanoscale CMOS technology.
  10. 2017. Microelectronics Reliability. Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process.
  11. 2017. IEEE Trans. Electron Devices. On-chip ESD protection device for high-speed I/O applications in CMOS technology.
  12. 2017. International Conference on Intelligent Informatics and BioMedical Sciences. High-voltage driving circuit with on-chip ESD protection in CMOS technology.
  13. 2016. IEEE Trans. Device and Materials Reliability. Diode string with reduced clamping voltage for efficient on-chip ESD protection.
  14. 2016. IEICE Electronics Express. Design of local ESD clamp for cross-power-domain interface circuits.
  15. 2016. IEEE Electron Device Letters. Low-leakage and low-trigger-voltage SCR device for ESD protection in 28-nm high-k metal gate CMOS process.
  16. 2016. Solid State Electronics. Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology.
  17. 2016. Invention Journal of Research Technology in Engineering & Management. SCR-based ESD protection designs for RF ICs.
  18. 2016. IEEE Trans. Electron Devices. Area-efficient and low-leakage diode string for on-chip ESD protection.
  19. 2015. IEEE Trans. Electron Devices. Improving ESD robustness of PMOS device with embedded SCR in 28-nm high-k/metal gate CMOS process.
  20. 2015. Microelectronics Reliability. Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-µm CMOS process.
  21. 2015. IEEE Trans. Device and Materials Reliability. Impact of inner pickup on ESD robustness of multi-finger MOSFET in 28-nm high-k/metal gate CMOS process.
  22. 2015. IEEE Trans. Electron Devices. Design of ESD protection device for K/Ka-band applications in nanoscale CMOS process.
  23. 2014. IEEE Trans. Microwave Theory and Techniques. Design of ESD protection diodes with embedded SCR for differential LNA in a 65-nm CMOS process.
  24. 2014. IEEE Trans. Device and Materials Reliability. Optimization on layout style of diode stackup for on-chip ESD protection.
  25. 2014. Analog Integrated Circuits and Signal Processing. Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process.
  26. 2014. IEEE J. Solid-State Circuits. A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control.
  27. 2013. IEEE Trans. Microwave Theory and Techniques. Large-swing-tolerant ESD protection circuit for gigahertz power amplifier in a 65-nm CMOS process.
  28. 2013. IEEE Trans. Device and Materials Reliability. Design of dual-band ESD protection for 24-/60-GHz millimeter-wave circuits.
  29. 2013. IEEE Trans. Biomedical Circuits and Systems. Implantable stimulator for epileptic seizure suppression with loading impedance adaptability.
  30. 2013. IEEE Trans. Electron Devices. Robust ESD protection design for 40Gb/s transceiver in 65nm CMOS process.
  31. 2012. IEEE Trans. Microwave Theory and Techniques. ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process.
  32. 2012. IEEE Trans. Device and Materials Reliability. Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology.
  33. 2012. Microelectronics Reliability. Investigation on CDM ESD events at core circuits in a 65-nm CMOS process.
  34. 2011. IEEE Trans. Device and Materials Reliability. Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies.
  35. 2011. Microelectronics Reliability. Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process.
  36. 2011. J. Neural Engineering. Stimulus driver for epilepsy seizure suppression with adaptive loading impedance.

  1. Test structures of LASCR device for RF ESD protection in nanoscale CMOS process. 必填欄位. International Conference on Microelectronic Test Structures.
  2. Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology. 必填欄位. Nanotechnology Materials and Devices Conference.
  3. On-chip ESD protection design for radio-frequency power amplifier with large-swing-tolerance consideration. 必填欄位. Asia Pacific Conference on Circuits and Systems.
  4. K-band low-noise amplifier with stacked-diode ESD protection in nanoscale CMOS technology. 必填欄位. International Symposium on Physical and Failure Analysis of Integrated Circuits.
  5. High-voltage driving circuit with on-chip ESD protection in CMOS technology. 必填欄位. International Conference on Intelligent Informatics and BioMedical Sciences.
  6. ESD protection design with low-leakage consideration for silicon chips of IoT applications. 必填欄位. International Conference on CYBER Technology in Automation, Control, and Intelligent Systems.
  7. ESD protection design for wideband RF applications in 65-nm CMOS process. 必填欄位. International Symposium on Circuits and Systems.
  8. Closed-loop stimulation and control of epileptic seizures in an implantable neural-prosthetic device. 必填欄位. International Brain Stimulation Conference.
  9. Circuit design of electrical stimulator realized in 0.18μm CMOS process for epileptic seizure suppression. 必填欄位. International Brain Stimulation Conference.
  10. Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology. 必填欄位. International Symposium on Physical and Failure Analysis of Integrated Circuits.
  11. ESD protection design for high-speed circuits in nanoscale CMOS process. . International Symposium on Integrated Circuits.
  12. ESD protection design for high-speed applications in CMOS technology. . International Midwest Symposium on Circuits and Systems.
  13. ESD protection design for gigahertz differential LNA in a 65-nm CMOS process. . Asia-Pacific International Symposium on Electromagnetic Compatibility.

研究計畫

  1. 2018. 創新無線通訊晶片之靜電放電防護技術開發(I).
  2. 2018. 應用於高速電路之創新靜電放電防護技術開發(3/3).
  3. 2017. 應用於高速電路之創新靜電放電防護技術開發(2/3).
  4. 2017. Latchup Prevention and ESD Protection Designs in Advanced CMOS Processes.
  5. 2017. 積體電路與電子系統之靜電放電防護技術產學聯盟(第二期)(1/3).
  6. 2017. 先進類比數位轉換技術.
  7. 2017. 次世代無線通訊晶片之靜電放電防護技術開發.
  8. 2016. 應用於高速電路之創新靜電放電防護技術開發(1/3).
  9. 2015. 神經電生理訊號與誘發肌電圖之量測晶片及電刺激器之研發(3/3).
  10. 2014. 前瞻性靜電放電防護技術開發.
  11. 2014. 神經電生理訊號與誘發肌電圖之量測晶片及電刺激器之研發(2/3).
  12. 2013. 神經電生理訊號與誘發肌電圖之量測晶片及電刺激器之研發(1/3).

  1. 2019. 面板級封裝抗靜電電路之設計與開發.
  2. 2019. ESD防護電路晶片佈局與量測.
  3. 2018. 靜電放電防護能力驗證.
  4. 2018. 應用於高速電路之創新靜電放電防護技術開發(3/3).
  5. 2017. 應用於高速電路之創新靜電放電防護技術開發(2/3).
  6. 2016. 應用於高速電路之創新靜電放電防護技術開發(1/3).
  7. 2015. 超高頻積體電路之靜電放電防護設計.
  8. 2014. 高壓CMOS製程之閂鎖防制設計.
  9. 2012. 積體電路之靜電放電防護設計.

其他

  1. 靜電放電防護電路及積體電路. 中華民國. 必填欄位. 必填欄位.
  2. 矽控整流器. 中華民國. 必填欄位. 必填欄位.
  3. 靜電防護電路及積體電路. 中華民國. 必填欄位. 必填欄位.
  4. 具有ESD防護之矽控整流器,以及製造用以做爲ESD防護電路之矽控整流器之方法. 中華民國. 必填欄位. 必填欄位.
  5. Electrostatic discharge protection circuit. 美國. 必填欄位. 必填欄位.
  6. Silicon controlled rectifier. 美國. 必填欄位. 必填欄位.
  7. ESD protection circuit and integrated circuit. 美國. 必填欄位. 必填欄位.
  8. Robust ESD protection with silicon-controlled rectifier. 美國. 必填欄位. 必填欄位.
  9. 具有合併觸發機制的靜電放電防護電路. 中國. 必填欄位. 必填欄位.
  10. 利用低壓元件實現的低漏電高壓電源靜電放電保護電路. 中國. 必填欄位. 必填欄位.
  11. 静電放電保護電路、結構及射頻接收器. 中國. 必填欄位. 必填欄位.
  12. 用於射頻發射機的静電放電電路. 中國. 必填欄位. 必填欄位.
  13. 具有合併觸發機制之靜電放電防護電路. 中華民國. 必填欄位. 必填欄位.
  14. 利用低壓元件實現的低漏電高壓電源靜電放電保護電路. 中華民國. 必填欄位. 必填欄位.
  15. 電流刺激裝置. 中華民國. 必填欄位. 必填欄位.
  16. 具負載適應性之生物電流刺激器. 中華民國. 必填欄位. 必填欄位.
  17. 具有多指矽控整流器之靜電保護電路. 中華民國. 必填欄位. 必填欄位.
  18. ESD protection circuitry with multi-finger SCRs. 美國. 必填欄位. 必填欄位.
  19. High-voltage-tolerant ESD clamp circuit with low leakage current fabricated by low-voltage CMOS process. 美國. 必填欄位. 必填欄位.
  20. Electrostatic discharge circuit for radio frequency transmitters. 美國. 必填欄位. 必填欄位.
  21. ESD protection circuit. 美國. 必填欄位. 必填欄位.
  22. Current stimulator. 美國. 必填欄位. 必填欄位.
  23. Electrostatic discharge protection circuit. 美國. 必填欄位. 必填欄位.
  24. Electrostatic discharge circuit using inductor-triggered silicon-controlled rectifier. 美國. 必填欄位. 必填欄位.
  25. Load-adaptive bioelectric current stimulator. 美國. 必填欄位. 必填欄位.

  1. ISSCC 2013 Distinguished Technical Paper Award. 2014/02. IEEE.