上一頁

專任教授


姓名

郭建宏

職稱

副教授

02-7749-3543

chk@ntnu.edu.tw

個人網站

研究專長

混合信號IC設計、類比數位轉換器、三角積分調變器、鎖相迴路、延遲鎖相迴路

研究成果

著作

  1. 2011. IET Electronic Letters. Floating Capacitor Switching SAR ADC.
  2. 2011. IEEE Transactions on Ultrasonics, ferroelectrics, and Frequency control. A Multi-Band Fast-Locking Delay-Locked Loop With Jitter-Bounded Feature.
  3. 2010. IEEE Transactions on Circuits and Systems I: Regular Papers. A Low-Voltage Fourth-Order Cascade Delta-Sigma Modulator in 0.18-mm CMOS.
  4. 2006. IEE Proceedings on Circuits, Devices and Systems. Magnetic Field to Digital Converter Using PWM and TDC Techniques.
  5. 2004. IEEE Sensors Journal. Magnetic-to Digital Converters Using Single-Amplifier-Based Second-Order Delta-Sigma Modulators.
  6. 2004. IEEE Journal of Solid-State Circuits. A 1-V 10.7MHz Fourth-Order Bandpass ΔΣ Modulators Using Two Switched Opamps.
  7. 2003. Analog Integrated Circuits and Signal Processing. A Sub-1V Fourth-Bandpass Delta-Sigma Modulator.
  8. 2003. IEEE Sensors Journal. CMOS Magnetic Field to Frequency Converter.
  9. 2002. Analog Integrated Circuits and Signal Processing. Multi-Bit Delta-Sigma Modulator Using a Modified DWA Algorithm.
  10. 2001. IEEE Journal of Solid-State Circuits. CMOS Oversampling ΔΣ Magnetic-to-Digital Converters.
  11. 2000. IEEE Journal of Solid-State Circuits. A Double-Sampling Pseudo-Two-Path Bandpass ΔΣ Modulator.

  1. A ΔΣ Modulator with 3-Bit, 37-Level Pre-Detective Dynamic Quantization. 2012/09/19. 10th IEEE International Conference on Semiconductor Electronics.
  2. A High Energy-Efficiency SAR ADC Based on Partial Floating Capacitor Switching Technique. 2011/09/12. IEEE the 37th European Solid-State Circuits Conference ESSCIRC.
  3. An All-Digital ΔΣ Envelope Modulator for EER-Based Transmitters Based on CMOS Standard Cell Design. 2011/06/26. The 9th IEEE International New Circuits and Systems Conference.
  4. A High-Order Sturdy MASH CIFF ΔΣ Modulator with Delaying Digital Feedforward Structure. 2010/08/03. The 21th VLSI Design/CAD Symposium.
  5. A Sixth-order 4–2 SMASH CIFF Complex Bandpass ΔΣ Modulator with Delaying Digital Input Feedforward. 2010/05/30. IEEE International Symposium on Circuits and Systems ISCAS 2010.
  6. An Ultra Low-Power Delta-Sigma Modulator Using Charge-Transfer Amplifier Technique. 2008/11/30. IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008.
  7. A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications. 2008/11/30. IEEE Asia Pacific Conference on Circuits and Systems APCCAS 2008.
  8. A Multi-Band Delay-Locked LOOP with Fast-Locked and Jitter-Bounded Features. 2008/11/03. IEEE Asian Solid-State Circuits Conference ASSCC 2008.
  9. A Third-Order Four-Bit Delta-Sigma Modulator with MCIFF Structure for Wideband Applications. 2008/08/18. The IASTED International Conference on Circuits and System.
  10. An Ultra Low-Voltage Multibit Delta-Sigma Modulator for Audio-Band Application. 2008/05/18. IEEE International Symposium on Circuits and Systems ISCAS 2008.
  11. A 0.8V SOP-Based Wideband Fourth-Order Cascade Delta-Sigma Modulator. 2007/08/08. The 18th VLSI Design/CAD Symposium.
  12. A Low-Power High-Gain Rail-to-Rail Input/Output Operational Amplifier. 2007/08/08. The 18th VLSI Design/CAD Symposium.
  13. A Fast-Locking DLL-Based Frequency Multiplier for Wide-Range Operation. 2007/07/02. The 5th IASTED International Conference on Circuits, Signals and Systems.
  14. A 91dB SOP-Based Low-Voltage Low-Distortion Fourth-Order 2-2 Cascaded Delta-Sigma Modulator. 2006/11/20. The 4th IASTED International Conference on Circuits, Signals and Systems.
  15. A 1V 82dB Multibit Delta-Sigma Modulator. 2006/08/08. the 17th VLSI Design/CAD Symposium.
  16. A 10-bit 2.5mW 0.27mm2 CMOS DAC with Spike-Free Switching. 2005/06/14. IEEE International Symposium on Consumer Electronics.
  17. A Tunable Bandpass ΔΣ Modulator Using Double Sampling Technique. 2005/05/23. IEEE International Symposium on Circuits and Systems 2005.
  18. A Frequency Synthesizer Using Two Different Delay Feedbacks. 2005/05/23. IEEE International Symposium on Circuits and Systems 2005.
  19. A Pipelined ADC with Digital Correction for IEEE 802.11a WLAN. 2005/05/11. The 5th WSEAS IMCCAS International Conference.
  20. A 2.5V 6.4mW 10-bit 140MS/s Digital-to-Analog Converter with Improved Current Mirror. 2005/05/11. The 5th WSEAS IMCCAS 2005 International Conference.
  21. CMOS Oversampling ΔΣ Magnetic to Digital Converters. 2001/05/06. IEEE International Symposium on Circuits and Systems ISCAS 2001.

研究計畫

  1. 2012. 具數位校正功能之高效率4G手機LTE射頻發射機-總計畫(2/3).
  2. 2012. 4G手機 LTE射頻發射機之高線性高性能數位信號調變器.
  3. 2011. 具數位校正功能之高效率4G手機LTE射頻發射機-總計畫.
  4. 2011. 具數位校正功能之高效率4G手機LTE射頻發射機-4G手機LTE射頻發射機之高線性高性能數位信號調變器(1/3).
  5. 2010. 多重行動電話標準之高效率極座標發射機-總計畫(2/2).
  6. 2010. 多重模式多頻段之數位類比轉換器設計(2/2).
  7. 2009. 多重模式多頻段之數位類比轉換器設計(1/2).
  8. 2009. 多重行動電話標準之高效率極座標發射機-總計畫(1/2).
  9. 2008. 具數位校正電路之低電壓三角積分調變器設計.
  10. 2007. 使用電荷傳輸放大器技術之超低功率類比數位轉換器設計.
  11. 2006. 0.9V以下低電壓應用於寬頻之低通三角積分調變器之研製.
  12. 2005. 0.9V低電壓多位元高解析度低通三角積分調變器之研製.
  13. 2005. 低功率高效能類比數位暨數位類比轉換器之研製(II).
  14. 2004. 低功率高效能類比數位暨數位類比轉換器之研製.

  1. 2010. 前瞻晶片系統SoC學程計劃.
  2. 2009. 前瞻晶片系統SoC學程計劃.
  3. 2008. 97年度前瞻課程發展計畫.

其他

  1. 可降低能量耗損之逐次逼近暫存式類比數位轉換器. 美國. 2011/09/22. 必填欄位.

  1. 2012大學校院積體電路設計競賽. 2012/04/26. 研究所類比電路設計. D級.
  2. 99學度大學校院積體電路設計競賽. 2011/04/28. 類比電路設計. 第三等/第三名或等同.
  3. 95學年度全國大專院校積體電路設計競賽. 必填欄位. 全客戶式設計. 其他.
  4. 2007年第七屆旺宏金矽獎,半導體設計應用大賽. 2007/07/01. 半導體設計與應用大賽. 第三等/第三名或等同.