Analog Devices Inc.(\u7c21\u7a31ADI)\uff0c\u70ba\u5168\u7403\u985e\u6bd4IC\u7b2c\u4e8c\u540d\u7684\u4f9b\u61c9\u5546\u3002\u81ea1965\u5e74\u5275\u5efa\u4ee5\u4f86\uff0c\u591a\u6b21\u88ab Fortune \u96dc\u8a8c\u7372\u9078\u70ba\u4e16\u754c\u4e94\u767e\u5927\u53ca\u7f8e\u570b\u524d\u4e00\u767e\u5927\u6700\u56ae\u5f80\u70ba\u5b83\u5de5\u4f5c\u7684\u4f01\u696d\uff0c\u4e14\u69ae\u767b\u5546\u696d\u9031\u520a\u5168\u7403\u6700\u4f73\u767e\u5927\u79d1\u6280\u516c\u53f8\u7b2c\u5341\u540d \u3002ADI\u8a2d\u8a08\u3001\u88fd\u9020\u3001\u884c\u92b7Mix Signal, Digital Signal Processors, D\/A, A\/D Converter \u9ad8\u529f\u80fd\u7a4d\u9ad4\u96fb\u8def\u7522\u54c1(ICs)\uff0cAnalog Devices\u7f8e\u5546\u4e9e\u5fb7\u8afe\u516c\u53f8\u662f\u5168\u7403\u7cbe\u5bc6\u9ad8\u6548\u80fd\u7a4d\u9ad4\u96fb\u8def\u7684\u9818\u5c0e\u5ee0\u5546\uff0c\u7522\u54c1\u5ee3\u6cdb\u7528\u5728\u985e\u6bd4\u548c\u6578\u4f4d\u8a0a\u865f\u8655\u7406\u61c9\u7528\u4e2d\u3002\u516c\u53f8\u7e3d\u90e8\u8a2d\u5728\u7f8e\u570b\u9ebb\u85a9\u8af8\u585e\u5dde\u8afe\u4f0d\u5fb7\u5e02\uff0c\u64c1\u6709\u54e1\u5de5\u7d0415,000\u4eba\uff0c\u88fd\u9020\u5ee0\u904d\u5e03\u4e16\u754c\u5404\u5730\u5728\u9ebb\u5dde\u3001\u52a0\u5dde\u3001\u611b\u723e\u862d\u3001\u83f2\u5f8b\u8cd3\u7686\u6709\u88fd\u9020\u5ee0\uff0cADI\u516c\u53f8\u7684\u80a1\u7968\u5728\u7d10\u7d04\u8b49\u5238\u4ea4\u6613\u6240\u4e0a\u5e02\uff0c\u4e26\u4e14\u7d0d\u5165\u6a19\u6e96\u666e\u723e\u6307\u6578500\u5bb6 (S&P 500 Index)\u3002 ADI \u7db2\u7ad9\uff1ahttps:\/\/www.analog.com<\/p>\n\n\n\n
(2026 New College Grad) Analog Design Engineer(Power)<\/p>\n\n\n\n
Tasks & Responsibilities <\/p>\n\n\n\n
Responsibilities may include but are not limited to:<\/p>\n\n\n\n
\u2022 Creating transistor-level analog circuits to meet performance specifications<\/p>\n\n\n\n
\u2022 Verifying designs using circuit-level and behavioral-level simulations<\/p>\n\n\n\n
\u2022 Supervising and reviewing circuit layout <\/p>\n\n\n\n
\u2022 Performing AMS simulations for top-level verification<\/p>\n\n\n\n
\u2022 Modeling DC-DC switching regulator behavior using Simplis or Verilog-A<\/p>\n\n\n\n
\u2022 Reading and understanding Verilog RTL code<\/p>\n\n\n\n
\u2022 Writing circuit documentation and test plan<\/p>\n\n\n\n
\u2022 Validating and debugging circuit performance in the lab<\/p>\n\n\n\n
\u2022 Collaborating with cross-functional teams including applications, test engineering, and other design groups. <\/p>\n\n\n\n
Qualifications & Skills <\/p>\n\n\n\n
\u2022 Minimum qualification: <\/p>\n\n\n\n
o Bachelor\u2019s degree in Electrical Engineering or related field <\/p>\n\n\n\n
o Strong understanding of analog IC design fundamentals <\/p>\n\n\n\n
o Solid knowledge of basic analog circuit topologies and layout principles <\/p>\n\n\n\n
o Effective written and verbal communication skills in English <\/p>\n\n\n\n
o Strong teamwork and collaboration skills<\/p>\n\n\n\n
\u2022 Preferred qualification: <\/p>\n\n\n\n
o Master\u2019s degree in Electrical Engineering or related field <\/p>\n\n\n\n
o Research experience related to IC design <\/p>\n\n\n\n
o Familiarity with Cadence design environment and analog simulation tools. <\/p>\n\n\n\n
o Experience with Simplis is a plus <\/p>\n\n\n\n
o Knowledge of Verilog-A, Verilog-AMS or WREAL modeling is a plus <\/p>\n\n\n\n
o Understanding of Verilog hardware description language is a plus <\/p>\n\n\n\n
o Proficiency in at least one scripting language (Python, shell-scripting, etc.).<\/p>\n\n\n\n